Array Logic Macros

A macro design approach is discussed which combines the cost-effective attributes of array logic structures with those of random logic. These macros utilize the following features: (a) internal feedback registers for performing sequential logic, (b) masking and submasking to reduce the number of words in the array for certain functions, (c) control of the array’s output level to vary the apparent size of the array, (d) decoding on input pairs and/or EXCLUSIVE oRing on output pairs for increasing the number of logic levels, and (e) random-access memory in the feedback and its use in interrupt handling. The macros are explained by specific design examples. This paper also discusses standard logic circuits in combination with an array structure to produce a component that can be used efficiently in specific data processing areas. The designer may elect to define an array logic macro which is a combination of some of the features given in this paper. The guideline for this selection is based upon the features necessary in an array structure to be competitive with a random logic LSI chip. Introduction The type of array logic considered in this paper is the dual array configuration [ I ] , where one array is a programmable decoder whose output selects words in the second array [Random Access Memory (RAM) array]. Each word in the decode array can be programmed to select its associated word in the RAM array. This selection is based upon matching the contents of the word with the input variables. The word may be programmed to match on each of the input variables being TRUE ( l ) , INVERTED (0), or DON’T CARE (0 or 1) . The decode word is a product (AND) term since the selection is based upon specific inputs being at a defined value. The DON’T CARE condition enables the decode array to select more than one word simultaneously. The RAM array generates the sum (OR) of all the selected words on its output. Thus, the function performed by the array logic considered in this paper is the sum of products. This type of Figure 1 The binary associative array. AND array OR array array is programmed to solve Boolean equations which are expressed in the form of sums of products. The number of variables that can be processed in the product is limited to the number of inputs to the decode array, while the number of sum terms is restricted to the number of words in the array. The purpose of this paper is (a) to show how this type of array logic solves specific problems in a data processing system, and (b) to demonstrate how minor modifications to this array can significantly expand the variety of its applications. The dual array structure has the same characteristics and circuits as an associative array. Throughout the remainder of this paper, the programmable decode array (which performs the product function) will be called the AND array; the RAM array (which performs the sum function) will be called the OR array. Features of array logic This section describes the features, operation, and attributes of array logic. The next section discusses additions to array logic for specific applications.